Ementa do Curso
This course presents the technology of Field-Programmable Gate Arrays (FPGA) by studying several representative architectures, their design tools, and their applications. The course presents also the architectures and tools of multi-FPGA systems within the context of emulation and reconfigurable computing. A highlight of the increasingly prominent role FPGAs play in system-on-chip (SOC) design is also part of this course.
After completion of this course:
· Students should have a firm understanding of FPGA technology and the relevant issues surrounding its use in system design.
· Students should have developed strong design skills necessary to synthesize and map a given design on an FPGA device using FPGA design tools.
· Students should be prepared to conduct fruitful research related to the architecture, tools, and applications of programmable logic.
- Introduction to Programmable Devices
- Types of Programmable Devices
- Programming Technologies
- Logic Cell Architectures
- Routing Architectures
- Low Energy FPGAs (Part-1)
- Low Energy FPGAs (Part-2)
- Self-Timed FPGAs (Part-1)
- Self-Timed FPGAs (Part-2)
- Virtex FPGAs (Part-1)
- Virtex FPGAs (Part-2)
- Reconfigurable Computing Systems (Part-1)
- Reconfigurable Computing Systems (Part-2)
- FPGA Digit-Serial Arithmetic (Part-1)
- FPGA Digit-Serial Arithmetic (Part-2)
- FPGA Digit-Serial Arithmetic (Part-3)
- Linear Feedback Shift Registers (Part-1)
- Linear Feedback Shift Registers (Part-2)
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- S. Trimberger, “Effects of FPGA architectures on FPGA routing”, ACM/IEEE Design Automation Conference, 1995, pp. 574-578.
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- E. Kusse, J. Rabey, “Low-energy embedded FPGA structures”, IEEE Int’l Symposium on Low Power Electronics and Design, 1998, pp. 155-160.
- V. George, H. Zhang, J. Rabaey, “The design of a low energy FPGA”, ACM Int’l Symposium on Low Power Design, 1999, pp. 188-193.
- A. Davis, S. M. Nowick, “An introduction to asynchronous circuit design”, September 1997.
- D. H. Linder, J. C. Harden, “Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry”, IEEE Transactions on Computers, vol. 45, no. 9, pp. 1031-1044, September 1996.
- C. Traver, R. B. Meese, M. A. Thornton, “Cell designs for self-timed FPGAs”, IEEE Int’l ASIC/SOC Conference and Exhibit, 2001, pp. 175-179.
- R. B. Reese, M. A. Thornton, C. Traver, “A fine-grain phased logic CPU”, IEEE CS Annual Symposium on VLSI, 2003, pp. 70-79.
- Xilinx, Inc., “Virtex-II Pro Introduction”, 2003.
- Xilinx, Inc., “Virtex-II Pro Functional Description”, 2003.
- K. Bondalapati, V. K. Prasanna, “Reconfigurable computing systems “, Proceedings of the IEEE, vol. 90, no. 7, pp. 1201- 1217, July 2002.
- A. DeHon, “Density advantage of configurable computing”, IEEE Computer, vol. 33, no. 4, pp. 41-49, Apr. 2000.
- H. Lee, G. E. Sobelman, “Performance evaluation and optimal design for FPGA-based digit-serial DSP functions”, Computers and Electrical Engineering, vol. 29, no. 2, pp. 357-377, March 2003.
- B. Dipert, “Shattering the programmable-logic speed barrier”, Electronic Design News (EDN), no. 16, August 1997.
- M. George, P. Alfke, “Linear feedback shift registers in Virtex devices”, Xilinx Application Note 210, 2001.
- S Lim, A. Miller, “LFSRs as functional blocks in wireless applications”, Xilinx Application Note 220, 2001.
- Z. Salcic, A. Smailagic, Digital Systems Design and Prototyping, Second Edition, Kluwer Academic Publishers, 2000.
- S. M. Trimberger, Field-Programmable Gate Array Technology, Kluwer Academic Publishers, 1994.
- S. D. Brown, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992.