FPGA Design

Fonte: Prof. Abdel Ejnioui (páginas de todos os professores)

Ementa do Curso

This course presents the technology of Field-Programmable Gate Arrays (FPGA) by studying several representative architectures, their design tools, and their applications. The course presents also the architectures and tools of multi-FPGA systems within the context of emulation and reconfigurable computing. A highlight of the increasingly prominent role FPGAs play in system-on-chip (SOC) design is also part of this course.

After completion of this course:

· Students should have a firm understanding of FPGA technology and the relevant issues surrounding its use in system design.
· Students should have developed strong design skills necessary to synthesize and map a given design on an FPGA device using FPGA design tools.
· Students should be prepared to conduct fruitful research related to the architecture, tools, and applications of programmable logic.


  1. Introduction to Programmable Devices
  2. Types of Programmable Devices
  3. Programming Technologies
  4. Logic Cell Architectures
  5. Routing Architectures
  6. Low Energy FPGAs (Part-1)
  7. Low Energy FPGAs (Part-2)
  8. Self-Timed FPGAs (Part-1)
  9. Self-Timed FPGAs (Part-2)
  10. Virtex FPGAs (Part-1)
  11. Virtex FPGAs (Part-2)
  12. Reconfigurable Computing Systems (Part-1)
  13. Reconfigurable Computing Systems (Part-2)
  14. FPGA Digit-Serial Arithmetic (Part-1)
  15. FPGA Digit-Serial Arithmetic (Part-2)
  16. FPGA Digit-Serial Arithmetic (Part-3)
  17. Linear Feedback Shift Registers (Part-1)
  18. Linear Feedback Shift Registers (Part-2)

Referências Bibliográfica

  1. S. Brown, J. Rose, “FPGA and CPLD architectures: A tutorial”, IEEE Design & Test of Computers, vol. 13, no. 2, pp. 42-57, Summer 1996.
  2. J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, “Architecture of field-programmable gate arrays”, Proceedings of the IEEE, vol. 81, no. 7, pp. 1013-1029, July 1993.
  3. S. Trimberger, “Effects of FPGA architectures on FPGA routing”, ACM/IEEE Design Automation Conference, 1995, pp. 574-578.
  4. J. Greene, V. Roychowdhury, S. Kaptanoglu, A. El Gamal, “Segmented Channel Routing”, ACM/IEEE Design Automation Conference, 1990, pp. 567-572.
  5. E. Kusse, J. Rabey, “Low-energy embedded FPGA structures”, IEEE Int’l Symposium on Low Power Electronics and Design, 1998, pp. 155-160.
  6. V. George, H. Zhang, J. Rabaey, “The design of a low energy FPGA”, ACM Int’l Symposium on Low Power Design, 1999, pp. 188-193.
  7. A. Davis, S. M. Nowick, “An introduction to asynchronous circuit design”, September 1997.
  8. D. H. Linder, J. C. Harden, “Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry”, IEEE Transactions on Computers, vol. 45, no. 9, pp. 1031-1044, September 1996.
  9. C. Traver, R. B. Meese, M. A. Thornton, “Cell designs for self-timed FPGAs”, IEEE Int’l ASIC/SOC Conference and Exhibit, 2001, pp. 175-179.
  10. R. B. Reese, M. A. Thornton, C. Traver, “A fine-grain phased logic CPU”, IEEE CS Annual Symposium on VLSI, 2003, pp. 70-79.
  11. Xilinx, Inc., “Virtex-II Pro Introduction”, 2003.
  12. Xilinx, Inc., “Virtex-II Pro Functional Description”, 2003.
  13. K. Bondalapati, V. K. Prasanna, “Reconfigurable computing systems “, Proceedings of the IEEE, vol. 90, no. 7, pp. 1201- 1217, July 2002.
  14. A. DeHon, “Density advantage of configurable computing”, IEEE Computer, vol. 33, no. 4, pp. 41-49, Apr. 2000.
  15. H. Lee, G. E. Sobelman, “Performance evaluation and optimal design for FPGA-based digit-serial DSP functions”, Computers and Electrical Engineering, vol. 29, no. 2, pp. 357-377, March 2003.
  16. B. Dipert, “Shattering the programmable-logic speed barrier”, Electronic Design News (EDN), no. 16, August 1997.
  17. M. George, P. Alfke, “Linear feedback shift registers in Virtex devices”, Xilinx Application Note 210, 2001.
  18. S Lim, A. Miller, “LFSRs as functional blocks in wireless applications”, Xilinx Application Note 220, 2001.

Leitura Adicional

  1. Z. Salcic, A. Smailagic, Digital Systems Design and Prototyping, Second Edition, Kluwer Academic Publishers, 2000.
  2. S. M. Trimberger, Field-Programmable Gate Array Technology, Kluwer Academic Publishers, 1994.
  3. S. D. Brown, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992.